Digital samples of e.g. video data to be displayed on a computer monitor is processed by a video graphics circuit, which has the task of both aligning samples provided by an asynchronous sampler, and blending those samples. Blending can involve changing the sampling rate of those samples, for example when the scale is to be varied. Thus the effect can be reduced resolution, and thus can be likened to the data passing through a low pass filter.
FIG. 1 is a block diagram that illustrates how sampling can be done. For example, the input samples of e.g. a video stream which have been sampled using an asynchronous clock are to be resampled so that they are synchronous with a reference clock. The reference clock is usually at a different phase than the sampling clock, and in a video signal, the reference is usually the horizontal sync edge. Thus, after sampling, the horizontal sync edge is used to assign fractional sample numbers to the asynchronously sampled samples. The circuit is then used to resample the samples in order to produce samples that can be numbered with integer sample numbers.
The input samples are applied to a one bit clock delay circuit 3. The input samples are multiplied in multiplier 5 with a data signal (1-x), where x represents the fractional part of the incoming sample number. The delayed input samples are multiplied in multiplier 7 with data signal x. The result data of the multiplication is added in adder 9, providing an output sample signal.
Let us assume that we have sampled a ramp in voltage such that the sample value is equal to the sample number. Assume that the input sample numbers and values are 100.1, 101.1, 102.1, 103.1, 104.1, and assume that the desired output sample numbers and values are 101.0, 102.0, 103.0, etc. The circuit described above interpolates between two samples (e.g. samples 101.1 and 102.1) to find the value for the sample 102.0.
The fractional part of the incoming sample number, x=0.1. The output of multiplier 7 is (100.1.times.0.1)=10.01 and the output of multiplier 5 is (101.1.times.0.9)=90.99. The output of adder 9 is 10.01+90.99=101. Similarly, for the next sample, the output of multiplier 7 is (101.1.times.0.1)=10.11 and the output of multiplier 9 is (102.1.times.0.9)=91.8; the output of adder 9 is 10.11+91.89=102. In this way the desired samples have been derived from the existing samples, the desired samples being aligned to the horizontal sync edge.
A horizontal scaler performs blending among two or more samples to better represent scaling, as distinguished from simply dropping samples. A blender produces fractional samples from samples that are integer numbered.
Scaling will be better understood from a consideration of FIG. 2, which is similar to FIG. 1 except for the factor which is multiplied by the input sample number and delayed sample number. The factor y which is multiplied in multiplier 5 with the input sample number is the fractional part of a requested sample number, and the factor which is multiplied with the delayed sample number is (1-y).
Thus for example, if the input sample numbers are 100.0, 101.0, 102.0, 103.0, etc., and the video graphics circuit is to scale down 1.5:1, then the output sample numbers would be numbered 100.0, 101.5, 103.0, 104.5, etc. The calculations to determine these are done as in the example given with reference to FIG. 1, since the circuits operate similarly.
It will be recognized that the scaler also degrades the resolution of the signal, and thus operates as a finite impulse response (FIR) low pass filter. Therefore in order to perform both sample aligning and scaling blending of a digital video signal, there are in effect two FIR low pass filters in series filtering the signal, which further degrade the signal, to an objectionable extent.